In this applications, a full Field Oriented Control (FOC) structure will be illustrated for a Permanent Magnets machine based electrical drive. First of all, the PM-machine exhibits sinusoidal back-EMF and it is equipped with an absolute position sensor: absolute encoder, resolver, etc…
It is assumed here that a resolver is available, being directly manageable by the PED-Board. Two or three phase currents can be read and sent to the abc-to-dq transformation. The implemented control scheme is highlighted in Figure 1 where saturations are not shown.
The RDC block is the Resolver-to-Digital converter that is controlled by the provided LabVIEW driver. However, the PED-Board resolver driver provides the speed and position as seen by the resolver which could have one or more lobes. From FOC point of view, the designer needs to know the PM-machine flux position and usually the electrical speed (ωe) for the evaluation of the decoupling terms. Mechanical speed ωm can be simply obtained from ωe by the machine pole-pairs.
Figure 1. Basic scheme of the implemented PMSM vector control.
Accordingly, the FPGA has to scale and shift the measured position that comes from the resolver unit. This task is performed by a proper chain as shown in Figure 2. Figure 2 shows also the usage of the PED-Board ADC1 driver and proper measure scaling. Over current (OVC), over voltage (OVV) and over speed (OVS) protection should be included as illustrated. As usual in FPGA applications, the control structure has been implemented using fixed-point arithmetic (FXP). Before using on a different drive, the user should check carefully numeric resolution, overflow and desired accuracy. Failt to do that, can result in unpredictible behaviors or damage of the electric drive.
Clarke and Park transformations, require the correct alignement of the flux vector. In this particular case, the phase A to neutral peak voltage corresponds to a position equals to zero. Moreover, phase sequence is A-B-C when the measured speed is positive. A typical oscillogram is shown in Figure 3 where the machine line-to-line voltages are superimposed to the aligned electrical position (Ch1). In this case, zero reference is 30 degress lagging the Vab voltage.
Position shifting operation is performed by the Single Cycle Timed Loop by changing the constant dTheta from zero (0°) to 4095 (360°). Only leading operations are allowed being dTheta a positive FXP number. After that, the new electrical rotor position is bounded from zero to 2π. Constant P/L is the ratio between the machine pole-pairs and the resolver lobes, which of course, must be an integer. Electrical rotor position, scaled and aligned, can be plot using the Digital-to-Analog Converter driver.
Figure 2. FPGA measures, speed and position scaling.
Figure 3. Machine L-L voltages and electrical position.
Inverter current is regulated with two separated PI-type controllers. In fact, thanks to the abc-to-dq reference change, the resulting dq-axes currents are theoretically DC quantities. Previously mentioned current controllers have been implemented inside the LabVIEW FPGA Single Cycle Timed Loop (SCTL) as shown in Figure 4. PI controllers can be reset and their output is saturated. However, the inverter voltage vector must be correctly saturated to avoid over-modulation effects. In this applications a 3rd harmonic injection feature is used, resulting in a normalized saturation of 1.15 (Vs_MAX). SubVIs reported in right-side of Figure 4, perform that task.
Of course, it results in a non-perfect WindUp of the PI controllers: controllers saturation is not affected by output voltage saturation (Dd and Dq).
It can be noticed from Figure 4, the true parallelism in the execution of the dq-axes controllers.
Integral and proportional gains can be selected in the s-domain as shown in [3]–[4]. Discretization is operated by the Real-Time target, and the resulting numerical values in z-domain are sent to the FPGA.
Figure 4. SCTL current controllers and output voltage vector saturation.
FPGA main scheduler
The role of the main scheduler is to correctly call the different tasks to be executed at a specific time (i.e. sampling frequency for control algorithms). In a classical DSP or μC applications, it is usually performed by the zero-overhead PWM unit. A fully programmable FPGA allows to realize the same structure in a very simple manner. If a center aligned PWM modulation scheme is desired, an up-down counter can be configured on the FPGA as shown in Figure 5. The main counter can be intended also as the carrier used to generate the inverter PWM pulses. The possibility to perform an undersamplig with respect to the main switching frequency can be obtained from an additional counter acting as frequency divider. The FIFO Item is used to call the execution of the main control loop: measure acquisition, scaling, regulation, etc…
Inverter switching frequency is selected by the Fsw variable and it must be evaluated in ticks at a specific clock. In order to increase the PWM resolution, a new clock domain has been created at 120 MHz (derived clock). Ticks derivation according to the desired Fsw is explained in the provided project and it is also reported as follow.
![\[ F_{sw} (ticks)=\frac{120\cdot 10^6 [Hz]}{2\cdot F_{sw} [Hz]} \]](https://www.ped-board.com/wp-content/ql-cache/quicklatex.com-2b93181ac2af675e941c33c29d3b1fb0_l3.png "Rendered by QuickLaTeX.com")
Figure 5 . FPGA main scheduler and PWM pulse generation.
RT target
In this application, the role of the RT target is to manage the Graphical User Interface (GUI), operate the discretization of the controllers parameters and allow the user to fully manage the electric drive.
Missing features
Some features are missing in this brief description as decoupling at the output of the current controllers and complete desaturation.
Project download
- PED-Board generic LabVIEW project (.LVPROJ) (LabVIEW 2015)
Fixed-point implementation, FXP
Project must be updated to PED-Board_CLIP_9.zip
References
[1] Wei Zhan; Porter, J.R.; Morgan, J.A., “Experiential Learning of Digital Communication Using LabVIEW,” in Education, IEEE Transactions on, vol.57, no.1, pp.34-41, Feb. 2014.
[2] Nguyen Khanh Quang; Nguyen Trung Hieu; Ha, Q.P., “FPGA-Based Sensorless PMSM Speed Control Using Reduced-Order Extended Kalman Filters,” in Industrial Electronics, IEEE Transactions on, vol.61, no.12, pp.6574-6582, Dec. 2014.
[3] Kshirsagar, P.; Burgos, R.P.; Jihoon Jang; Lidozzi, A.; Fei Wang; Boroyevich, D.; Seung-Ki Sul, “Implementation and Sensorless Vector-Control Design and Tuning Strategy for SMPM Machines in Fan-Type Applications,” in Industry Applications, IEEE Transactions on, vol.48, no.6, pp.2402-2413, Nov.-Dec. 2012.
[4] Lidozzi, A.; Serrao, V.; Solero, L.; Crescimbini, F.; Di Napoli, A., “Direct Tuning Strategy for PMSM Drives,” in Industry Applications Society Annual Meeting, 2008. IAS ’08. IEEE , pp.1-7, 5-9 Oct. 2008.
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